VHDL port map和reg/wire

uut_fifo : ipcore_fifo_256x8 port map(
clk    =>  clk            , 
rst    =>  rst            ,
din    =>  gub_data_out    ,
wr_en  =>  gub_fifo1_wr    ,
rd_en  =>  gub_fifo1_rd    ,
dout   =>  fifo1_mux1_data  ,
full   =>  open           ,
empty  =>  open           
       );

http://blog.sina.com.cn/s/blog_4bbcda6d0100i248.html