Clock Buffer Basics
Clocksare the basic building blocks for all electronics today. For every datatransition in a synchronous digital system, there is a clock that controls aregister. Most systems use Crystals, Frequency Timing Generators (FTGs), orinexpensive ceramic resonators to generate precision clocks for theirsynchronous systems. Additionally, clock buffers are used to create multiplecopies, multiply and divide clock frequencies, and even move clock edgesforwards or backward in time. Many clock-buffering solutions have been createdover the past few years to address the many challenges required by today’shigh-speed logic systems. Some of these challenges include: High operating andoutput frequencies, propagation delays from input to output, output to outputskew between pins, cycle-to cycle and long-term jitter, spread spectrum, outputdrive strength, I/O voltage standards, and redundancy. Because clocks are thefastest signals in a system and are usually under the heaviest loads, specialconsideration must be given when creating clocking trees. In this chapter, weoutline the basic functions of non-PLL and PLL-based buffers and show how thesedevices can be used to address the high-speed logic design challenges.
Intoday’s typical synchronous designs, multiple clock signals are often needed todrive a variety of components. To create the required number of copies, a clocktree is constructed. The tree begins with a clock source such as an oscillatoror an external signal and drives one or more buffers. The number of buffers istypically dependent on the number and placement of the target devices. Figure2.1 illustrates the concept of the clock tree.
Inyears past, generic logic components were used as clock buffers. These wereadequate at the time, but they did little to maintain the signal integrity ofthe clock. In fact, they actually were a detriment to the circuit. As clocktrees increased in speed and timing margins reduced, propagation delay andoutput skew became increasingly important. In the next several sections, wediscuss the older devices and why they are inadequate to meet the needs oftoday’s designs. The definitions of the common terms associated with modernbuffers follow. Finally, we address the attributes of the modern clock bufferwith and without a PLL. The FTG that is often used as a clock source is aspecial type of PLL clock buffer. A discussion of these devices can be found inChapter 12.
Figure 2.1 Typical ClockTree
EarlyBuffers: A clock buffer is a device in which the output waveform follows theinput waveform. The input signal propagates through the device and is re-drivenby the output buffers. Hence, such devices have a propagation delay associatedwith them. In addition, due to differences between the propagation delaythrough the device on each input-output path, skew will exist between theoutputs. An example of a non-PLL based clock buffer is the 74F244 that is available from severalmanufacturers. These devices have been available for many years and weresuitable for designs where frequencies were below 20 MHZ. Designers would bringin a clock and fan it out to multiple synchronous devices on a circuit card.With these slow frequencies and associated rise times, designers had suitablemargins with which to meet setup and hold times for their synchronousinterfaces. However, these buffers are not optimal for today’s high-speedclocking requirements. The 74F244suffers from a long propagation delay (3 to 5 ns) and long output-to-outputskew delays. Non- PLL based clock buffers have improved in recent years and usemore advanced I/O design techniques to improve the output-to-output skew. Asthe clock period gets shorter, the uncertainty or skew in the clockdistribution system becomes more of a factor. Since clocks are used to drivethe processors and to synchronize the transfer of data between systemcomponents, the clock distribution system is an essential part of the systemdesign. A clock distribution system design that does not take skew intoconsideration may result in a system with degraded performance and reliability.
ClockSkew: Skew is the variation in the arrival time of two signals specified tooccur at the same time. Skew is composed of the output skew of the drivingdevice and variation in the board delays caused by the layout variation of theboard traces. Since the clock signal drives many components of the system, andsince all of these components should receive their clock signal at preciselythe same time in order to be synchronized, any variation in the arrival of theclock signal at its destination will directly impact system performance. Skewdirectly affects system margins by altering the arrival of a clock edge.Because elements in a synchronized system require clock signals to arrive atthe same time, clock skew reduces the cycle time within which information canbe passed from one device to the next. As system speeds increase, clock skewbecomes an increasingly large portion of the total cycle time. When cycle timeswere 50 ns, clock skew was rarely a design priority. Even if skew was 20% ofthe cycle time, it presented no problem. As cycle times dropped to 15 ns andless, clock skew requires an ever-increasing amount of design resource. Nowtypically, these high-speed systems can have only 10% of their timing budgetdedicated to clock skew, so obviously, it must be reduced.
Thereare two types of clock skew that affect system performance. The clock drivercauses intrinsic skew and the printed circuit board (PCB) layout and design isreferred to as extrinsic skew. Extrinsic skew and layout procedures for clocktrees will be discussed later in this book. The variation of time due to skewis defined by the following equation:
tSKEW _INTRINSIC = Device Induced Skew
tSKEW_EXTRINSIC = PCB + Layout + Operating Environment Induced Skew
tSKEW = t SKEW_INTRINSIC + t SKEW_EXTRINSIC
Intrinsicclock skew is the amount of skew caused by the clock driver or buffer byitself. Board layout or any other design issues, except for the specificationstated on the clock driver data sheet do not cause intrinsic skew.
OutputSkew: Output skew (TSK) is also referred to as pin-to-pin skew. Output skew isthe difference between delays of any two outputs on the same device atidentical transitions. Joint Electronic Device Engineering Council (JEDEC)defines output skew as the skew between specified outputs of a single devicewith all driving inputs connected together and the outputs switching in thesame direction while driving identical specified loads. Figures 2.2 and 2.3show a clock buffer with common input CIN driving outputs Co1_1 through Co1_n.The absolute maximum difference between the rising edges of the outputs will bespecified as output skew. Typical output skew in today’s high performance clockbuffers is around 200 picoseconds (PS).
Figure 2.2 Clock BufferModel
Figure 2.3 Clock BufferSkew
Part-to-PartSkew: Part-to-part skew (TDSK) is also known as package skew anddevice-to-device skew. Part-to part skew is similar to output skew except thatit applies to two or more identical devices. Part-to-part skew is defined asthe magnitude of the difference in propagation delays between any specifiedoutputs of two separate devices operating at identical conditions. The devicesmust have the same input signal, supply voltage, ambient temperature, package,load, environment, etc. Figure 2.4 illustrates TDSK from the preceding example.Typical part-to-part skew for today’s high performance buffers is around 500ps.
Figure 2.4 Part-to-PartSkew
PropagationDelay: Propagation delay (TPD) is the time between specified reference pointson the input and output voltage waveforms with the output changing from onedefined level (low) to the other (low). Propagation delay is illustrated inFigure 2.3. Non-PLL based devices in today’s high performance devices rangefrom 3 to 7 ns. PLL-based buffers are able to zero out this propagation delaywith the aid of Phase Detectors, Loop Filters and Voltage ControlledOscillators (VCOs).
UnevenLoading: When using a high-speed clock buffer or PLL, care must be taken toequally load the outputs of the device to ensure that tight skew tolerances aremaintained. Inherent in each output of the clock driver is output impedancethat is mostly resistive in nature (along with some inductance andcapacitance). When each of these resistive outputs is equally loaded, the tightskew specification of the clock driver is preserved. If the loads becomeunbalanced, the (RC) time constants of the various outputs would be different,and the skew would be directly proportional to the variation in the loading.
InputThreshold Variation: After the low skew clock signals have been distributed,the clock receivers must accept the clock input with minimal variations. If theinput threshold levels of the receivers are not uniform, the clock receiverswill respond to the clock signals at different times creating clock skew. Ifone load device has a threshold of 1.2 volts and another load device has athreshold of 1.7 volts and the rising edge rate is 1V/ns, there will be 500psof skew caused by the point at which the load device switches based on the inputsignal. Most manufacturers center the input threshold level of their devicesnear 1.5 volts nominal for (TTL) input devices. This input threshold will varyslightly from manufacturer to manufacturer especially as conditions (such asvoltage and temperature) change. The TTL specification for the input thresholdlevel is guaranteed to be logic high when the input voltage is above 2.0 voltsand a logic low when the input voltage level is below 0.8 volts. This leaves a1.2-volt window over voltage and temperature. Components with ComplementaryMetal Oxide Semiconductor (CMOS) rail swing inputs have a typical inputthreshold of VCC/2 or about 2.5 volts, which is much higher than the TTL level.If the threshold levels are not uniform, clock skew will develop betweencomponents because of these variations. There are many I/O standards which haveemerged and all must be taken into consideration when providing clocks todifferent subsystems. Table 2.1 listed below which lists the more prevalentstandards along with the input threshold voltages.
Table2.1 Input Threshold Voltages
Non-PLLBased Clock Drivers: There are two main types of modern clock driverarchitectures: a buffer-type device (non- PLL) and a feedback-type device(PLL). In a buffer-style (non-PLL) clock driver, the input wave propagatesthrough the device and is “re-driven” by the output buffers. This output signaldirectly follows the input signal and has a propagation delay (TPD) that rangesfrom 5 ns to over 15 ns. These devices differ from the buffers in the past suchas the 74F244 in that they are designed specifically for clocksignals. On a 74F244,there are eight inputs and eight outputs. To create a one to eight buffer, alleight inputs are tied together. This causes excess loading at the inputs on thedriving signal. A one to eight clock buffer has only one input and hence onlyone load. The output rise and fall times are also equally matched and thereforedo not contribute to duty cycle error. With their improved I/O structure, thepin-to-pin skew is kept to a minimum. The output skew of this device, if it isnot listed on the data sheet, can be calculated by subtracting the minimumpropagation delay from the maximum propagation delay.
Figure 2.5 Basic Buffer
The10 ns t PD clock driver delay shown in Figure 2.5 does not take into accountthe affects of the board layout and design. These types of devices areexcellent for buffering source signals such as oscillators where the outputphase does not need to match the input. A variety of the non-PLL based buffersis available on the market today and typically range from as few as 4 outputsto as many as 30. Some devices also include configurable I/O and internalregisters to divide the output frequencies. Among the highest performancenon-PLL based Low Voltage CMOS (LVCMOS) clock buffers available today is the B9940L. The B9940L is a low-voltage clock distribution buffer withthe capability to select either a differential LVPECL or a LVCMOS/LVTTLcompatible input clock. The two clock sources can be used to provide for a testclock as well as the primary system clock. All other control inputs areLVCMOS/LVTTL-compatible. The eighteen outputs are 2.5V - or 3.3V-compatible andcan drive two series terminated 50-Ohm transmission lines. With thiscapability, the B9940L has aneffective fan out of 1:36. Low output-to-output skews of 150ps, a device todevice skew of 750ps, and a high-end operating frequency of 200 MHz, makes theB9940L an ideal clockdistribution buffer for nested clock trees in synchronous systems. Thesedevices still face the problems of device propagation delay. The propagationdelay through these devices is about 5 ns. This delay will cause skew insystems where both the reference clock to the buffer and the outputs of thebuffer need to be aligned. These devices also have the drawback that the outputwaveform is directly based on the input waveform. If the input waveform is anon-50% duty-cycle clock, the output waveform will also have a less-than-idealduty cycle. Expensive crystal oscillators with tight tolerances are needed whenusing this type of buffer in systems requiring near 50/50 outputs. Thesedevices also lack the ability to phase adjusts or frequencies multiply theiroutputs. Phase adjustment allows the clock driver to compensate for tracepropagation delay mismatches and setup and hold time differences, and frequencymultiplication allows the distribution of high and low frequency clocks fromthe same common reference. Expensive components and time-consuming boardrouting techniques must be used to compensate for the functional shortcomings ofthese buffer-style clock driver devices. PLL-based devices have beenincorporated to address all of these shortcomings.
PLL-BasedClock Drivers: The second type of clock distribution device uses a feedbackinput that is a function of one of its outputs. The feedback input can beconnected internally or externally to the part. If it’s an external feedback, atrace is used to connect an output pin to the feedback pin. This type of deviceis usually based upon one or more PLLs that are used to align the phase andfrequency of the feedback input and the reference input. Since the feedbackinput is a reflection of an output pin, the propagation delay is effectivelyeliminated. In addition to very low device propagation delay, this type ofarchitecture enables output signals to be phase shifted to compensate forboard-level trace-length mismatches. Outputs can be selectively divided,multiplied, or inverted while still maintaining very low output skew.
PLLshave a number of desirable properties that include the ability to multiplyclock frequencies, correct clock duty cycles and cancel out clock distributiondelays. Many PLL based clock buffers have been brought to market in recentyears to aid clock tree designs that require zero propagation delay from theinput signal to the output. A completely integrated PLL allows alignment inboth the phase and the frequency of the reference with an output. We will lookat some of the more prevalent PLL-based clock buffers and their features in thefollowing sections.
Whatis a PLL: The basic PLL is a feedback system that receives an incomingoscillating signal and generates an output waveform that oscillates at the samefrequency as the input signal. It is comprised of a phase/frequency detector(PD), a low-pass filter, and a voltage-controlled oscillator as shown in Figure2.6. In order for the PLL to align the reference (REF) input with an output,the output must be fed back to the input of the PLL. This feedback (FB) inputis used as the alignment signal on which all other outputs are based.
Figure 2.6 PLL BlockDiagram
ThePhase Frequency Detector (PD) evaluates the rising edge of the REF input withrespect to the FB input. If the REF input occurs before the FB input indicatingthat the VCO is running too slowly, the PD produces a Pump Up signal that lastsuntil the rising edge of the FB input. If the FB input occurs before the REFinput, the PD produces a Pump Down signal that is triggered on the rising edgeof the FB input and lasts until the rising edge of REF. This Pump Down pulseforces the VCO to run slower. In this way, the PD forces the VCO to run fasteror slower based on the relationship of the REF and FB inputs. The output of theVCO is the internally generated oscillator waveform. The input voltage thatcontrols the frequency of the VCO is a measure of the input frequency — as theinput frequency changes so does this voltage. The PLL is designed to operatewithin a limited band of frequencies. If the input frequency is outside thisband, the circuit wills not lock-on to the input signal and FREF and FOUT willbe different. As long as FREF remains within the tracking range of the circuit,FOUT = FREF. However, if FREF moves out of range, the circuit goes out of lock,and once again the input and internal frequencies will be different. In theabsence of a REF input, the condition of the output is device-specific. Forinstance, with the loss of a reference input, the Cypress CY2308 ZDB willstri-state all outputs. However, the outputs of the CY7B991V operate at thedevice’s slowest speed while the outputs of the CY7B994V will run at theirhighest frequency. Therefore, the specifics of the device need to be known ifthe design will be placed in this condition. (There are now buffers thatsupport dual clock inputs if the loss of an input clock is expected.) Thefilter converts these Pump Up and Pump Down signals into a single controlvoltage (FCONT) and its magnitude is dependent on the number of previous PumpUp and Pump Down pulses that have occurred. The range of the voltage producedby the filter is guaranteed to force the VCO into any frequency within theselected frequency range.
ZeroDelay Buffer: A zero delay buffer (ZDB) is a device that can fan out one clocksignal into multiple clock signals with zero delay and very low skew betweenthe outputs. This device is well suited for a variety of clock distributionapplications requiring tight input-output and output-output skews. A simplifieddiagram of a ZDB is shown in Figure 2.7. A ZDB is built with a PLL that uses areference input and a feedback input. The feedback input is driven by one ofthe outputs. The phase detector adjusts the output frequency of the VCO so thatits two inputs have no phase or frequency difference. Since the PLL controlloop includes one of the outputs and its load, it will dynamically compensatefor the load placed on that output. This means that it will have zero delayfrom the input to the output that drives feedback independent of the loading onthat output. Note that this is only the case for the output being monitored bythe Feedback input and all other outputs have an input to output delay that isaffected by the differences in the output loads. Please see the section “Leador Lag Adjustment” for a discussion of this topic. The Cypress SemiconductorCY2308 is a dual bank, general purpose ZDB providing eight copies of a singleinput clock with zero delay from input to output and low skew between outputs.This popular buffer is designed for use in a variety of clock distributionapplications and will be used throughout this book as the typical Zero Delay,PLL-based buffer. The capability to externally connect the feedback path on thedevice provides skew-control and opens up opportunities for some interestingapplications.
Leador Lag Adjustments: Lead can be defined as the output of the buffertransitioning earlier in time than the input reference signal. It can also beviewed as negative delay. Lag, on the other hand, is the output clocktransitioning later in time than the input and is a positive delay. To adjustthe lead or lag of the outputs on the CY2308, we must understand therelationships between REF and FBK, and the relationship between the outputdriving FBK and the other outputs. First, we need to understand a fewproperties of PLLS. The PLL senses the phase of the FB pin at a threshold ofVDD/2 and compares it to the REF pin at the same VDD/2 threshold. All theoutputs start their transition at the same time (including the output drivingFBK).
Figure 2.7 CY2308 PLLClock Buffer
Changing the load on an output changes its rise time and therefore how longit takes the output to get to the VDD/2 threshold. Using these properties toour advantage, we can then adjust the time when the outputs reach the VDD/2threshold relative to when the REF input reaches the VDD/2 threshold. Theoutput driving FB however cannot be adjusted; it will always have zero delayfrom the REF input at VDD/2. Loading the output used for the feedback moreheavily can advance in time the other outputs. The other outputs can also bedelayed in time by loading the output for the feedback more lightly than theother outputs. Figure 2.8 shows how many picoseconds the outputs are movedversus the difference in the loading between the feedback output and the otheroutputs. As a rough guideline, the adjustment is 50 PS/pF of loading difference.Note that the ZDB will always adjust itself to keep the VDD/2 point of theoutput at zero delay from the VDD/2 point of the reference. If the applicationrequires the outputs of the zero delay buffer to have zero delay from anotheroutput of the reference clock chip, the output of the clock chip that isdriving the ZDB must be loaded the same way as the other outputs of the clockchip or the outputs of the ZDB will be advanced/delayed with reference to thoseother outputs. Adding additional capacitance beyond 30pF is not suggested dueto the possibility of degrading the clock edges and adding more jitter to theoutputs. Adjusting the lead or lag of the output skew with a capacitor has itsbenefits. However, it does have imperfections because of variations in thecapacitor itself. For small delay adjustments, it is more precise to use tracedelay that matches the needed lead or lag times. For larger amounts of delay, aprogrammable skew device such as the CY7B994V should be considered.
Figure 2.8 Lead/LagAdjustments
UsingExternal Feedback: Many ZDBs have an open external feedback path that is simplyclosed by driving any output into the FB pin for ZDB operation. However, thefeedback path can be used for other interesting applications. Using a discretedelay element in the feedback path will generate outputs that lead the inputsignal. Sometimes designs require some copies of a clock that are earlycompared to the remaining copies of the input clock. Figure 2.9 shows a circuitimplementation to generate such early clocks using a ZDB.
Figure 2.9 Early Clocks
Figure 2.10 Trace SkewAdjustments
Anothersimple approach to lead or lag output clocks is to insert trace delay into thefeedback path. The outputs of the buffer will lead the input by the amount oftrace delay added in the feedback path. This approach provides a precise methodfor delay adjustment. Some designers will embed a very long trace into theboard from an output pin to the feedback pin. At the ends of each trace segment,the designer places pads for zero ohm resistors. This allows for incrementaladditional delay into the feedback path to align the outputs to the precisephase. Figure 2.10 shows an example where the feedback path is 5 inches shorterthan the other output traces. This initially allows the remaining outputs to belater in time than the input. By placing a capacitor on the feedback line, theoutputs can be moved forward in time.
FrequencyMultiplier: By using an external divider in the feedback path we can alsocreate a frequency multiplier out of a simple ZDB. As shown in Figure 2.11, an/N divider in the feedback path will cause all outputs to run at a frequencywhich is N times the input frequency. Whatever the multiplication factor, inputand output frequencies must be in the range of the PLL.
Figure 2.11 FrequencyMultiplier
SpecialtyApplication Clock Buffers: This chapter has focused primarily on general purposeclock drivers and zero delay buffers. However, there are a number of clockbuffers available that have been designed to fit the requirements of particularsubsystems that require precision clocking. For example, there are devices withfrequencies that comply with specific standards such as MPEG video and T1communication, and a variety of other specifications. There are also clockcomponents designed to address a particular application. An example of this isthe SDRAM clock buffer. DDR SDRAMs uses double data rate architecture toachieve high-speed operation. The double data rate architecture is essentiallya 2n-prefetch architecture with an interface designed to transfer two datawords per clock cycle at the I/O pins. A single read or write access for theDDR SDRAM consists of a single 2n-bit wide, one-clock-cycle data transfer atthe internal DRAM core and two corresponding n-bit wide, one-half-clock-cycledata transfers at the I/O pins. Very specific clocking requirements have beenspecified by JEDEC to ensure proper operation of these DDR SDRAMs. DDR SDRAMsrequire high-speed SSTL- 2 clocking solutions and the v857 has emerged tosupport these requirements. The v857 is offered by many vendors and is ahigh-performance, low-skew, low-jitter PLL clock driver. It takes one pair of differential input signals and fans out to 10 pairs ofdifferential output with low skew and low jitter at SSTL-2 voltage levels. Alldata inputs and outputs are SSTL_2 level compatible with JEDEC standard forSSTL-2 and can drive up to 14 DDR SDRAM loads.
DifferentialClocks: There are two common electrical methods totransmit data from a source to a destination. One method uses a “single-ended”signaling concept that makes use of two conductors between the transmitter andreceiver. It uses a dedicated signal-line to send the signal from transmitterto receiver and a common ground return shared by all signals. The other methodis a differential signaling where true and complement forms of the signal aresent from the transmitter to the receiver.While this also uses two conductors between the transmitterand receiver, they now both carry active signals and neither is shared withother signals. Differential signaling usestwice as many signal lines as a single-ended signaling.Differential signaling has a number of important advantages over thesingle-ended signaling because of the abilityof the differential receiver to reject any signal that is common to both lines. This ability is commonlyreferred to as common-mode noise rejection.The common mode rejection occurs because the receiver is only sensitive to a difference between the two inputs. When the twodifferential paths are closely linked, the noisewill be apparent on both signals and rejected at the destination. With a singleended approach, the external noise will beapparent on the signal line itself. Because the differentialsignaling method rejects the common- mode noise signals, lower voltage levels can be used for reliable transmission of serialdata. An additional benefit from the lower voltagesused for differential signaling is reduced comparable power levels. Differential PECL, LVPECL and LVDS clocks havebecome quite popular means of clocking high-speedlogic in recent years.
PECLBuffers: As clock speeds increase above 100 MHz, noise immunity is ofparticular concern. PECL and LVPECL clocks are particularly good for clockinghigh-speed devices. More and more devices are starting to require PECL clockinputs to drive their logic. Framers, SERIALIZER / DESERIALIZER (SERDES),Switch Fabrics and FPGAs are among the latest devices supporting PECL andLVPECL inputs. LVPECL stems from emitter coupled logic (ECL) but uses apositive rather than a negative supply voltage. It also uses 3.3 volt powersupply rather than 5V. The ECL VDD and VEE pins have traditionally been poweredfrom a –5.2V supply, VDD being grounded and VEE set at –5.2V where the intentis to achieve the lowest VDD noise by grounding the VDD pins. In more recentdesigns, however, ECL is often used with +5.0V instead of –5.2V and is commonlyreferred to as PECL (VDD set to +5.0V and VEE tied to ground). Since VDD noiseis not a major concern, this permits the use of a standard logic supply. Asclock speeds rise beyond 100 MHz, the advantages of using ECL and PECL becomemore obvious. Most of these advantages involve the use of differential signaltransmission. Differential signals are less susceptible to ground noiseproblems as all noise becomes common-mode. Single-ended CMOS is much moresusceptible, since ground bounce and other noise affect logic thresholds,degrading noise immunity. Logic levels are less critical in differentialsignaling as the threshold can tolerate significant signal attenuation.Differential circuits also tend to generate less noise in the power supply. ECLis designed with termination resistors that allow high-frequency signals topropagate with minimal overshoot and reflection.
A newseries of ZDB are becoming available that support LVPECL. The LVPECLdifferential driver is designed for low-voltage, high frequency operation toover 400 MHZ. It significantly reduces the transient switching noise and powerdissipation when compared to conventional single-ended drivers.
LVDSBuffers: LVDS (Low Voltage Differential Signaling) has become a popular meansof transporting binary data across boards and backplanes in recent years asnumerous low cost data buffers and FPGAs have begun to support thistransmission scheme. To achieve high data rates and keep power requirementslow, LVDS uses a differential voltage swing of only 350 mV (typical, inpoint-to-point applications). Furthermore, the LVDS CMOS current-mode driverdesign greatly reduces quiescent power supply requirements. LVDS data and clockbuffers have rapidly emerged to support this standard as defined inTIA/EIA-644.
SpreadAware Buffers: The use of Spread Spectrum Timing (SST) technology has beenpopular in the motherboard and printer markets for some time. It is being usedin virtually all motherboard designs using chipsets that support greater than100-MHz busses. Spread spectrum timing signals are used in a variety ofapplications including PCI, CPU, and memory buses. Nearly all motherboardchipset vendors are designing their parts to work with spread spectrum timingsignals. While the fast-paced motherboard market has quickly adopted thetechnology, it has also been embraced by other markets. The technology wasdeveloped solely for the purpose of reducing peak EMI. Spread spectrum timingis a very effective tool for reducing EMI and may be easily integrated intomany different systems without affecting other circuit elements. The one typeof circuit element that may cause a timing problem when driven by a SpreadSpectrum timing signal is a downstream PLL. A downstream PLL is a device thatreceives a reference timing signal from another PLL-based device, includingthose that use SST technology. “Downstream” may also apply to PLLs within Clockand Data Recovery (CDR) circuits. In a CDR application, the ability to properlytrack a modulated serial data stream is critical for clock extraction. For thisreason, tracking skew is very important in downstream PLL applications. A ZDBused on a memory module to buffer the clock signal and provide the correcttiming to latch the data could be considered as a likely downstream PLL.Although these devices may work properly with very stable reference inputs, ifthey cannot track a dynamically changing input signal, the output timingsignals will not be synchronized to the system timing. Clock buffers that cantrack the variations of a spread spectrum input are said to be “spread aware.”Spread Aware ZDBs are specifically designed to receive a spread spectrummodulated input signal. The PLL characteristics of Spread Aware devices willtrack the frequency modulation on the input signal with minimal accumulatedtracking skew. Therefore, spread spectrum modulation present on the ZDB inputsignal would also be present on the output signals.
Thiswill reduce the EMI emissions of the system. In addition, since the PLLtracking skew has been minimized, the system designer will have the benefit ofthe greatest possible timing margins.
WhichOne to Choose: The clock circuit is usually critical to the operation of thesystem. If the clock circuit fails, the system fails. Because of this, theproper selection of the clock driver/buffer is usually critical to the successor failure of the design. When selecting the clock driver/buffer there areseveral parameters and characteristics for which the designer can watch toensure the correct and reliable operation of the system. Since clock driverstend to operate at high frequencies, it is important to ensure that the clockdriver has low power dissipation. Unlike a buffer or latch that changes stateonly when one of the inputs changes, every output on the clock driver changesstate every clock cycle at the fastest rate available in the system. This meansthat the clock driver is most likely switching more power in a smaller packagethan any other component in the system. While heat sinks and other coolingmethods will help, it is best to start with a clock buffer/driver thatinherently dissipates low power. Choosing between a clock buffer or PLL isusually dependent upon the need for zero delay in the driver or the need to increasethe clock frequency. If zero delay or increased frequency is needed, a PLL isthe obvious choice. An advantage of a PLL over a buffer is the ability tocorrect the duty cycle in the clock line if there is distortion.
Conclusion:As system clocking speeds increase, the issues of skew and noise begin toreceive primary consideration. Increasing the clock frequencies and requiringtighter tolerances in the clocking circuits will achieve future gains in systemperformance. Low skew clock buffers and PLL clock drivers will assist thedesigner in meeting the system requirements for speed, skew and noise. However,the clock circuit must be designed as a clocking system with considerationgiven to all aspects of the clock distribution network including the driver,receivers, transmission lines and signal routing. If the designer is aware ofthe problems that can develop, the difficulties can be avoided. The best methodto identify the clock tolerances is to create a timing budget. The timingbudget identifies the effects that each element of the tree has on the clocksignals. The next chapter discusses the timing budget in detail.