Chisel（一）初识

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这个夏天，一个很奇妙的机会，突然触碰到一个全新的东西，那就是Chisel。首先感谢  _iChthyosaur的博客 https://blog.csdn.net/qq_34291505/article/details/86744581给予的平台让我第一次接触到这个新鲜的东西，我决定继续开始自己的学习之旅，这个系列的博客也不会是简单的转述，还是有自己的思考，初次接触一定还是会有很多理解上的问题，希望大家共同讨论共同进步。

初次接触Chisel，自然先去了解一下这个东西是什么东西

Chisel是什么？

Chisel（读作[ˈtʃi:zɔːl]），全名ConstructingHardwarein aScalaEmbeddedLanguage，是由伯克利开发的硬件构建语言，开源。

官网：https://chisel.eecs.berkeley.edu/index.html

下面是官网上列出的一些特性：

硬件构造语言（非HLS）

嵌入在Scala编程语言中

抽象的数据类型和接口

层次化+面向对象+功能化构造

用Scala中的标记来高度参数化

多时钟域

大量的标准库，包括浮点单元

针对ASIC和FPGA产生低层次的Verilog代码

github开源，BSD License

什么叫硬件构建语言？是来代替Verilog/SystemVerilog的吗？

Chisel可以简单的理解成高度抽象的、高度参数化的Verilog生成器，利用Scala语言的语法糖，来快速高效的开发硬件设计。设计完成后，自动生成Verilog，再经由传统的数字IC设计方法（逻辑综合、APR）变成芯片。

我们注意几点：

Chisel是基于Scala，也可以说Chisel是用Scala语言写的针对硬件开发的库。用Chisel语言做设计就是在写Scala语言的程序。有点类似UVM是SystemVerilog语言的验证框架库。

Chisel的应用专注在前端设计，提高设计的效率。

生成的Verilog是低层次的，也就是类似门级的。

目前仍然通过DC或者Genus来综合。

与HLS有明显区别，不能直接变成工艺相关的门级电路。也许以后会增加这种功能，得看相关EDA的发展。

那Chisel相比Verilog有什么优势？

抽象程度高、高度参数化

前端设计周期缩短

可以走敏捷开发流程

除了可以生成Verilog，还可以生成C/CPP。

都说Chisel开发快，那具体有哪些语法特性？

各种变量类型可以转换

位宽可以自动推断

与Verilog一样可以方便的取位和拼接

加减法可以防溢出

可以检查敏感信号列表，防止生成latch

可以以黑盒子的方式调用Verilog，或者以in-line的方式嵌入Verilog

灵活高效的接口定义，再也不需要AUTOARG

可以定义多套不同的实现，比如FPGA和ASIC定义不同的RAM

可以处理多时钟域，处理异步信号的同步

而这样介绍Chisel：

Chisel (Constructing Hardware In a Scala Embedded Language) is a hardware construction language embedded in the high-level programming language Scala. At some point we will provide a proper reference manual, in addition to more tutorial examples. In the meantime, this document along with a lot of trial and error should set you on your way to using Chisel. Chisel is really only a set of special class definitions, predefined objects, and usage conventions within Scala, so when you write Chisel you are actually writing a Scala program that constructs a hardware graph. However, for the tutorial we don't presume that you understand how to program in Scala. We will point out necessary Scala features through the Chisel examples we give, and significant hardware designs can be completed using only the material contained herein. But as you gain experience and want to make your code simpler or more reusable, you will find it important to leverage the underlying power of the Scala language. We recommend you consult one of the excellent Scala books to become more expert in Scala programming.

首先Chisel是含于高级语言Scala之中，而且 Chisel实际上只是Scala中的一组特殊类定义，预定义对象和使用约定，因此当您编写Chisel时，您实际上正在编写构建硬件图的Scala程序

Through the tutorial, we format commentary on our design choices as in this paragraph. You should be able to skip the commentary sections and still fully understand how to use Chisel, but we hope you'll find them interesting.

We were motivated to develop a new hardware language by years of struggle with existing hardware description languages in our research projects and hardware design courses. Verilog and VHDL were developed as hardware simulation languages, and only later did they become a basis for hardware synthesis. Much of the semantics of these languages are not appropriate for hardware synthesis and, in fact, many constructs are simply not synthesizable. Other constructs are non-intuitive in how they map to hardware implementations, or their use can accidently lead to highly inefficient hardware structures. While it is possible to use a subset of these languages and still get acceptable results, they nonetheless present a cluttered and confusing specification model, particularly in an instructional setting.

However, our strongest motivation for developing a new hardware language is our desire to change the way that electronic system design takes place. We believe that it is important to not only teach students how to design circuits, but also to teach them how to design circuit generators ---programs that automatically generate designs from a high-level set of design parameters and constraints. Through circuit generators, we hope to leverage the hard work of design experts and raise the level of design abstraction for everyone. To express flexible and scalable circuit construction, circuit generators must employ sophisticated programming techniques to make decisions concerning how to best customize their output circuits according to high-level parameter values and constraints. While Verilog and VHDL include some primitive constructs for programmatic circuit generation, they lack the powerful facilities present in modern programming languages, such as object-oriented programming, type inference, support for functional programming, and reflection.

Instead of building a new hardware design language from scratch, we chose to embed hardware construction primitives within an existing language. We picked Scala not only because it includes the programming features we feel are important for building circuit generators, but because it was specifically developed as a base for domain-specific languages.

对于如何使用Chisel表达

While Chisel focuses on binary logic, Chisel can support analog and tri-state wires with the Analog type - see Datatypes in Chisel.

We focus on binary logic designs as they constitute the vast majority of designs in practice. Tri-state logic are poorly supported standard industry flows and require special/controlled hard macros in order to be done.

 

在说Chisel之前首先说Scala语言，Scala是一门基于JVM运行的语言，他与JAVA语言相互兼容，Scala也是一门面向对象的函数式语言。

而现在对于主流的硬件描述语言还是Verilog，而Verilog一直以来也是有开发效率低下的弊病。后来对于这个的问题的讨论结果是对Verilog进行改良，也就出现了Verilog的后续标准——SystemVerilog，但是由于它只是用于验证。但是当时除了改良还有一部分人主张把语言转移到软件语言，（C++、Java），支持C++的诞生了SystemC，而对于Chisel就是支持Java的那部分人创造出的

是由加州大学伯克利分校的研究团队发布的一种新型硬件语言。据团队成员之一Krste Asanovic教授介绍，早在30多年前还没有硬件描述语言的时候，他们就已经开始构想这样一种语言了。最开始Chisel是基于Ruby的，但是后来发现Scala更适合构建Chisel。因为Scala有诸多特性适合描述电路，比如它是静态语言，以编译期为主，适合转换成Verilog/VHDL。再比如它的操作符即方法、柯里化、纯粹的面向对象、强大的模式匹配、便捷的泛型编写、特质混入、函数式编程等特性，使得用Scala开发DSL语言很方便。通过firrtl编译器可以把Chisel文件转换成firrtl文件，这是一种标准的中间交换格式，也就是让各种高级语言方便地转换到Verilog/VHDL的媒介，但它其实和verilog/VHDL属于同一层次。在这里，Chisel选择了妥协，没有直接生成电路，而是借助Verilog，主要是因为没有EDA工具支持，因此，它并不等同于HLS(High Level Synthesis)。将来也许会有EDA工具直接支持Chisel。

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