FPGA问题记录之：Warning (13024): Output pins are stuck at VCC or GND
陶星辰
FPGA问题记录之：
Warning (13024): Output pins are stuck at VCC or GND
Warning (21074): Design contains 16 input pin(s) that do not drive logic
硬件平台：Cyclone IV E EP4CE10F17C8
开发平台：Quartus II 64-Bit Version 13.0.1 Build 232 06/12/2013 SP 1 SJ Full Version
实验项目：vga_colorbar
实验模块：vga_ctrl
问题代码
module vga_ctrl
(
input wire vga_clk , //输入工作时钟,频率 25MHz
input wire sys_rst_n , //输入复位信号,低电平有效
input wire [15:0] pix_data , //输入像素点色彩信息
output wire [9:0] pix_x , //输出有效显示区域像素点 X 轴坐标
output wire [9:0] pix_y , //输出有效显示区域像素点 Y 轴坐标
output wire hsync , //输出行同步信号
output wire vsync , //输出场同步信号
output wire [15:0] vga_rgb //输出像素点色彩信息
);
//parameter define
parameter H_SYNC = 10'd96 , //行同步
H_BACK = 10'd40 , //行时序后沿
H_LEFT = 10'd8 , //行时序左边框
H_VALID = 10'd640 , //行有效数据
H_RIGHT = 10'd8 , //行时序右边框
H_FRONT = 10'd8 , //行时序前沿
H_TOTAL = 10'd800 ; //行扫描周期
parameter V_SYNC = 10'd2 , //场同步
V_BACK = 10'd25 , //场时序后沿
V_TOP = 10'd8 , //场时序上边框
V_VALID = 10'd480 , //场有效数据
V_BOTTOM = 10'd8 , //场时序下边框
V_FRONT = 10'd2 , //场时序前沿
V_TOTAL = 10'd525 ; //场扫描周期
//reg define
reg [9:0] cnt_h ; //行同步信号计数器
reg [9:0] cnt_v ; //场同步信号计数器
//wire define
wire rgb_valid ; //VGA有效显示区域
//cnt_h:行同步信号计数器
always@(posedge vga_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_h <= 10'd0;
else if(cnt_h == H_TOTAL - 1'd1)
cnt_h <= 10'd0;
else
cnt_h <= cnt_h + 1'd1;
//hsync:行同步信号
assign hsync = (cnt_h <= H_SYNC - 1'd1) ? 1'b1 : 1'b0;
//cnt_v:场同步信号计数器
always@(posedge vga_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_v <= 10'd0;
else if((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL - 1'd1))
cnt_v <= 10'd0;
else if(cnt_v == V_TOTAL - 1'd1)
cnt_v <= cnt_v + 1'd1;
else
cnt_v <= cnt_v;
//vsync:场同步信号
assign vsync = (cnt_h <= V_SYNC - 1'd1) ? 1'b1 : 1'b0;
//rgb_valid:VGA 有效显示区域
assign rgb_valid = ((cnt_h >= (H_SYNC + H_BACK + H_LEFT))
&&(cnt_h < (H_SYNC + H_BACK + H_LEFT + H_VALID)))
&&((cnt_v >= (V_SYNC + V_BACK + V_TOP))
&&(cnt_v < (V_SYNC + V_BACK + V_TOP + V_VALID)))
? 1'b1 : 1'b0;
//pix_data_req:像素点色彩信息请求信号,超前 rgb_valid 信号一个时钟周期
// assign
//pix_x,pix_y:VGA有效显示区域像素点坐标
assign pix_x = (rgb_valid == 1'b1)
? (cnt_h - (H_SYNC + H_BACK + H_LEFT)) : 10'b0;
assign pix_y = (rgb_valid == 1'b1)
? (cnt_v - (V_SYNC + V_BACK + V_TOP)) : 10'b0;
//vga_rgb:输出像素点色彩信息
assign vga_rgb = (rgb_valid == 1'b1) ? pix_data : 16'b0;
endmodule
报错信息：
Warning (13024): Output pins are stuck at VCC or GND
Warning (21074): Design contains 16 input pin(s) that do not drive logic
啊啊啊啊啊啊啊，排查了一个小时的错误。果然写代码时要细心啊！！！
//cnt_v:场同步信号计数器
else if((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL - 1'd1))
cnt_v <= 10'd0;
else if(cnt_v == V_TOTAL - 1'd1) //此处条件写错
cnt_v <= cnt_v + 1'd1;
改为：
else if((cnt_v == V_TOTAL - 1'd1) && (cnt_h == H_TOTAL - 1'd1))
cnt_v <= 10'd0;
else if(cnt_h == H_TOTAL - 1'd1) //此处条件写错，扫描完一行后(即cnt_h达最大)场计数加一
cnt_v <= cnt_v + 1'd1;
//vsync:场同步信号
assign vsync = (cnt_h <= V_SYNC - 1'd1) ? 1'b1 : 1'b0; //要细心啊，越图快越易错
改为：
assign vsync = (cnt_v <= V_SYNC - 1'd1) ? 1'b1 : 1'b0;
问题解决。
总结：
1.出现
Warning (13024): Output pins are stuck at VCC or GND
Warning (21074): Design contains 16 input pin(s) that do not drive logic
一般情况下就是代码编写出错。
2.特别是图快时复制粘贴相似变量代码段然后进行修改处容易出错。
3.排查步骤总结
根据报错信息
Warning (13024): Output pins are stuck at VCC or GND
Warning (13410): Pin "pix_x[0]" is stuck at GND
...
定位到相应变量（pix_x）：
output wire [9:0] pix_x , //输出有效显示区域像素点 X 轴坐标
在定位到对应变量（pix_x）的幅值语句：
assign pix_x = (rgb_valid == 1'b1)
? (cnt_h - (H_SYNC + H_BACK + H_LEFT)) : 10'b0;
检查赋值语句是否有误，无误则继续排查赋值语句中的其他变量(cnt_h，rgb_valid )，如赋值语句中判断语句中变量cnt_h的赋值语句：
//cnt_h:行同步信号计数器
always@(posedge vga_clk or negedge sys_rst_n)
if(sys_rst_n == 1'b0)
cnt_h <= 10'd0;
else if(cnt_h == H_TOTAL - 1'd1)
cnt_h <= 10'd0;
else
cnt_h <= cnt_h + 1'd1;
若无误则继续排查rgb_valid的赋值语句 ：
//rgb_valid:VGA 有效显示区域
assign rgb_valid = ((cnt_h >= (H_SYNC + H_BACK + H_LEFT))
&&(cnt_h < (H_SYNC + H_BACK + H_LEFT + H_VALID)))
&&((cnt_v >= (V_SYNC + V_BACK + V_TOP))
&&(cnt_v < (V_SYNC + V_BACK + V_TOP + V_VALID)))
? 1'b1 : 1'b0;
若无误则继续排查rgb_valid赋值语句中判断语句中变量cnt_h,cnt_v的赋值语句，cnt_h已排查，则只需排查cnt_v，最终找到cnt_v赋值语句中的问题。
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