vera

1. Install vera .  The version I used is 6.2.8
2. Create a template .
   (1), edit a top module with verilog . Surppose the name is test.v
   (2), Create a template .
        vera -tem -t test -c clk_i test.v
   (3), chang the interface and others
   (4). compile the vera, and get the test.vshell
        Vera –cmp –vlog test.vr
       
   (5). complie the verilog file with the test.vshell
        VCS –vera test.v test.test_top.v test.vshell
   (6). add other vera file . Suppose the name is disp.vr
        Simv +vera_load=disp.vr
   (7). ok
3. modelsim and ncverilog can compile the verilog with vera file . Please refer to the example in the vera installation directory .

:)