signature=abcea710e8925522bb7987d7b1618edd,Method and system for dynamically clocking digital system...

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENT

[0056] Aspects of the current invention are drawn to a system that monitors the current being drawn from a circuit or groups of circuits. Based upon the current draw of the system, an adaptable clocking circuitry regulates the clocking signals to an attached digital circuitry. In this manner, single circuits, or groups of circuits, may be adaptively clocked

[0057] The adaptive clocking may be accomplished through inhibiting clocking signals, or through adaptively slowing them, or some combination thereof. Additionally, the trigger level may be adaptively controlled through high-level intervention such as a processor, controller, or other digital signal. Additionally, a system mode signal may used in conjunction with the power levels to adaptively regulate the clock signal to any individual circuit or digital system, or any groups of circuits or systems.

[0058] FIG. 1 is a schematic block diagram of an adaptively clocked digital circuitry system according to the invention. An adaptive clocking mechanism can be manufactured on a chip containing digital logic circuits, controllers, or programmable processors that require a clock. Such a chip may be a digital system, or several chips may be combined in a digital system such as a computer, hand help digital device, smart card, or any other digitally operated system. Each of the extraneous logical functions is adaptively clocked. When the other portions of the system are in use, the power used by the complete system may go higher than the power consumption constraints allow. The drawn power problem is compounded when the system is powered by an electric battery. In this case, the maximum allowable power drawn on clock cycles may be far less than maximum allowable power levels seen when powered by conventional wall powered units.

[0059] The system contains a logic unit 10. The logic unit may be any digital circuitry requiring or using a clock signal. Or, it may be any digital circuitry in which the input is a clock.

[0060] The logic unit 10 provides logical functions to a system. In this case, when the system is running at a lower computational rate, the system can run at a high clock rate without breaching the total current or power consumption budget. When the overall powered to the system reaches a high level, the logic unit 10 can go into a slower mode, to conserve power or current draw during high usage times.

[0061] To adaptively clocked accomplish this, an adaptable clocking circuitry 20 is provided. The adaptively clocked circuit 20 monitors the total system current. The fast system clock is also input to the adaptively clocked circuit 20. When the system current reaches a threshold, the clock is adaptively slowed to the logic unit 10. In this manner, active power conservation is achieved for the system by selectively regulating the clock speed of logic unit 10.

[0062] For example, assume that the system is operating at a power load less than the maximum output. In this case, the adaptively clocked circuit determines that the steady current to the system allows for the full clocking of the logic unit 10. In this case, assume that the clock speed is set to 500 Mhz. In the steady state of the system, the full clock cycle of 500 Mhz would be delivered to the logic unit 10. However, assume that, for some reason, the system current exceeds a preset threshold. In this case, the adaptively clocked circuit 20 would limit the clock cycles to the logic unit 10.

[0063] Additionally, the adaptively clocked circuit 20 may be used in conjunction with modal circuitry to selectively screen circuitry based on priority as well as power consumption. In this manner, the adaptively clocked circuit may determine that the power load exceeds a threshold making the limiting of power necessary. The adaptively clocked circuit would then initially limit the clock cycles to the logic unit 10.

[0064] However, the mode of the actual circuitry may such that the circuitry may need to be run at the absolutely fastest speed. The adaptively clocked circuit 20 may then reset the clock signal to the fastest speed possible.

[0065] As such, the adaptively clocked circuit 20 may deterministically decide two threshold states for the clock to be limited to the circuitry. First, the power level of the actual system may be utilized to limit the clock cycles. Then, priority levels may be set in the circuitry to override the limitation, resulting in a resumption of the fastest clock cycle. As such, clock cycles can be adaptively set for multiple groups of circuits depending on power and on state.

[0066] All the logic circuits on a single chip may be regulated by a single adaptively clocked circuit. Alternatively, select circuitry on the chip may be regulated by the adaptively clocked circuit.

[0067] Or, in a complex system, such as a notebook computer, several bus attachments, such as a graphics adapter or input device such as a keyboard, may be regulated by such an adaptively clocked circuit. Individual chips on individual cards may be regulated by a single adaptively clocked circuit, or several chips on a single card may also be regulated by such an adaptively clocked circuit.

[0068] FIG. 2 is a block level diagram of an aspect of the adaptively clocked circuit of FIG. 1. In this aspect, the adaptively clocked circuit 22 is coupled to the system power supply. The adaptively clocked circuit 22 contains a system power monitor 24, a clock regulator 26, and an optional modal circuitry 28. When the system power supply is at or above a threshold value, the adaptively clocked circuit 22 determines that this state exists through the power monitor 24.

[0069] The power monitor 24 compares the present power supply characteristics to a threshold. When the threshold is met or exceeded, the clock regulator or clock generator 26 then limits the outgoing clock to the attached digital circuitry, As such, the adaptively clocked circuit 22 regulates the current consumed by the attached logic circuitry based on the system power or current consumption characteristics.

[0070] In one case, the clock regulator 26 will suppress the clock signal. In this case, the clock regulator 26 actively inhibits any clock signal to the attached logical circuitry. Only when the indication from the power monitor 24 indicates that the power supply to the system has fallen below a threshold will clock cycles be relayed to the rest of the attached digital logic.

[0071] Or, the clock regulator can slow the clock signal. In this case, when the power monitor indicates the power to the system has exceeded a threshold, it may latch the incoming clock to a clock division circuitry. In this manner, the clock is slowed by a predetermined amount.

[0072] When the power supply has fallen below the upper limits, the clock divisor may be deactivated, resulting in the resumption of the unregulated clock to the attached digital circuitry. As such, clock cycles to the attached circuitry may be “dropped” as long as the power levels exceed a threshold, or they may be limited by some sort of clock division circuitry.

[0073] Accordingly, many types of clock divisions schemes may be envisioned or directly designed. Many ratios can be affected, and can be designed into the circuit.

[0074] In one case, the power monitor 24 not only indicates that the power level has been exceeded, but may indicate how much the level has been exceeded by. For example, assume that the power monitor 24 indicates that the system current level, which triggers a slowdown, has been exceeded by a certain level.

[0075] The power monitor 24 reports to the adaptively clocked circuit 26 not only the fact that the current level has exceeded the upper limit, but may indicate by how much. In this case, the adaptively clocked circuit 26 will take the appropriate action based on how much the level has been exceeded by.

[0076] The adaptively clocked circuit may transform the clocking from a 1:1 ratio into a 3:2 ratio when one level is indicated. If a higher level is indicated, it may dynamically increase the ration to 2:1, and so on. If still a higher level is indicated, the full inhibition of the clocking may take place.

[0077] Possibly present on or about the adaptively clocked circuit 22 is a modal circuitry. This modal circuitry may be used to change or override the inhibition or reduction circuitry. In the simplest case, the modal circuitry may be a signal line from some portion of the entire system indicating that the logic of the attached circuitry is critical to the ongoing functionality. When this happens, the modal circuitry may be used to override the inhibition signal that may be generated.

[0078] As an example, the power monitor 24 may indicate that the level of current to the entire system is at or beyond a predetermined level. In this case, the power monitor would indicate to the adaptively clocked circuit 26 to divide or inhibit the clock to the circuitry.

[0079] If the modal circuitry indicates that the functionality of the attached digital circuitry is essential to the process, the combination of the signal from the power monitor 24 and the modal circuitry 28 may be logically combined together. In this manner, the clock mode of the circuitry functionality may be kept at a certain level.

[0080] In this case, the modal circuitry is used to override the inhibiton or reduction of the clock cycles. The mode may be used in multistate power determinations to enhabce or decrease the level at which the clocking regulation occurs. As such, the mode may be used to override, ehance, or diminish the adaptive clocking features.

[0081] FIG. 3 is a schematic diagram of an exemplary aspect of a power monitor circuitry of FIG. 2. In this case, the power monitor circuitry is a simple comparator. A digital representation of the entire system circuitry is derived and input into a comparator circuitry. A predetermined level is the second input to the comparator circuitry. When the first level is higher than the fixed reference voltage, the comparator outputs a signal indicative of this. In this manner, the output signal may be used to directly inhibit the output clock to the attached digital circuitry. Or, the output may be used to initiate a clock divisor circuitry.

[0082] FIG. 4 is a schematic diagram of a possible implementation of a power monitor according to FIG. 3 working in conjunction with an inhibition circuitry. In this case, the power monitor has indicated that the threshold level has been exceeded. The output of the comparator is latched into a D flip-flop. The other input to the D flip-flop is the regular clock. The output of the flip-flop is ORed with the clock itself.

[0083] When the power level has not exceeded the preset maximum, the output of the comparator is low, and the output of the D flip-flop is low. As such, in the normal state, the output of the OR gate is simply the clock itself.

[0084] However, when the level of the input to the comparator exceeds the fixed level, the comparator goes high. When the D flip-flop is clocked, the flip-flop will also go high. When this happens, the output of the OR gate goes high. The output of the OR gate will remain high for as long as the level coming into the comparator remains above the threshold. As such, the output clock is inhibited completely until the current level goes low.

[0085] The usage of the D flip-flop may preserve the clocking characteristics of the digital circuitry. In this manner, the edges of the clock are maintained in a synchronous manner. However, when synchronous edges are not needed, the output of the comparator may be directly ORed with the system clock.

[0086] FIG. 5 is a schematic diagram of a possible implementation of a power monitor according to FIG. 3 may be used to reduce, but not inhibit, the clocking signal to the attached digital circuitry. In this case, the power monitor takes the form as in the previous figure.

[0087] The output of the comparator goes to an input of a counter. The other input of the counter is the system clock. When the comparator output is high, the counter is enabled. The output of the counter is a fixed ratio of the input clock. The output of the counter, or the “slowed” clock, is ANDed with the output of the comparator. As such, the “slowed” clock is present on the output when the comparator is enabled, and a logical zero is on the output when the comparator is disabled.

[0088] The inverse of the comparator is also ANDed with the normal system clock. In this case, the output on this portion of the circuitry is a logical zero the comparator is asserted and the normal system clock when the comparator is deasserterd. The two outputs of the AND gates are ORed together. Thus, when the comparator goes high, the output is a reduced clock. When the comparator indicates a state that allows the full clocking of the attached digital circuitry, the output is the normal clock.

[0089] FIG. 6 is a schematic diagram of a possible power monitor circuitry that indicates how the supply may be monitored for differing levels in FIG. 2. In this case, the power level indication is fed directly into an analog to digital converter. The one analog input goes into the converter having multiple output line. The level of the power supply is then converted into a digital representation. These output lines may be used in conjunction with one another to activate the differing responses to the differing power levels.

[0090] FIG. 7 is schematic diagram of implementation of differing clock response to differing power levels, using the power monitor circuitry of FIG. 6. In this case, assume that the power level produces an indication on the line 40, indicative of the highest order bit on the converter. In this case, the assertion of this line is fed into an OR gate.

[0091] At the other input, the OR gate has a modified clock, which will be described below. However, when the line 40 is asserted, the output of the OR gate is an inhibition of the clocking functionality to the attached digital circuitry until the output of the line goes down.

[0092] When the output of the line 40 is low, the output of the OR gate is the modified clock signal emanating from clock modifying circuitry 42. Thus, when the high order bit is deasserterd, the output of the OR gate to the attached digital circuitry is the modified clock signal emanating form clock modifying circuitry 42.

[0093] Clock modifying circuitry 42 is made in a manner and havinag similar functionality as that depicted in FIG. 5. In this manner, when a line 44, indicating the middle bit of the converter circuitry is asserted, the output of the clock modifying circuitry 42 is a slowed clock, such as that described in FIG. 5. When the line 44 is deasserterd, the output of the clock modifying circuitry 42 is the normal system clock.

[0094] As such, when the first level is reached, the adaptively clocked circuit clocks the attached digital circuitry in a normal manner. However, when a first level is reached, the adaptively clocked circuit clocks the attached digital circuitry in a slower manner.

[0095] When a higher level of system power or current consumption is reached, the adaptively clocked circuit inhibits all clocking to the attached digital circuitry. Of course, various logical combinations of the pins or circuitry associated with the various significant digits of the multilevel detection circuitry may be used in combination to produce various results.

[0096] FIG. 8 is an alternative power monitor circuitry that may be used in the monitoring of different levels of system power or current consumption. In this case, three separate comparators are used. However, three differing reference voltages are used in each comparator. As such, the various consumption levels may be directly monitored in a static manner.

[0097] FIG. 9 is a schematic block diagram of the implementation of the modal circuitry in conjunction with the adaptively clocked circuit of FIG. 4. In this manner, a mode indicator is used as an input to an AND gate. The other input to the AND gate is a signal indicating the status of the attached digital circuitry with respect to the processing state of the system.

[0098] If the modal signal is deasserterd, then the output of the flip-flop is inhibited. As such, the overall inhibition signal may itself be inhibited based on the state of the system. Of course, such modal circuitry may be used in conjunction with those circuitries found throughout this specification. Such modal circuitry may be used to inhibit or restrict the “cloaking” of the system clock, or to restrict the “slowing” of the clock as well.

[0099] In one case, with the multiple clocking scheme of FIG. 7, the modal signal may be used to keep the slowing of the clock from happening, but the assertion of the inhibition signal may override the modal indication. Or, the modal indication may override all slowing and cloaking of the clocking signal. Of course, the modal signal may comprise various lines, indicating various levels of priority. In this manner, various combinatorial signals may be derive involving various stages of power level indicators along with modal indicators to produce a specific clocking outcome.

[0100] The levels at which events occur may also be dynamically altered. For example, in one case, the fixed reference voltages of FIGS. 3 and 8 may be variable reference voltage comparators. In this case, various control lines may be used to “set” the reference voltages at which events occur. For example, in FIG. 3, assume that the reference voltage is set a level A. When the control line 50 is asserted, the reference rises to a level B. Thus, the system can dynamically change the voltage giving rise to the “trigger” of the clock altering mechanisms. In one case, the modal circuitry may be used to set a higher threshold. This may occur with or without the combinatorial characteristics of the modal circuitry described above.

[0101] FIG. 10 is an exemplary aspect of a dynamic control circuit working in conjunction with an exemplary power monitor of FIG. 1. In this case, the main system voltage regulator supplies a small current to the adaptively clocked circuit 52. This small current is proportional to the current being drawn by the internal power output of the regulator. This signal is fed to an integrating capacitor. As such, the integral of the current over time is the voltage measured at the capacitor. As such, the voltage at the capacitor is indicative of the amount of current being drawn by the internal power supply.

[0102] The voltage of this capacitor may serve as the reference in any of the exemplary aspects depicted in the preceding specification. In normal operation, assume that the reference level of the triggering mechanism or mechanisms is at a voltage level y, indicative of a current y′ at the capacitor.

[0103] However, attached to the node of the capacitor is a programmable current sink 54. The programmable current sink 54 is in turn connected to a digital control signal. When the digital signal indicates one state, the programmable current sink will sink a set amount of current, x′. Thus, the total current into the attachment node between the programmable current sink 54 and the capacitor must be x′+y′. However the voltage of the capacitor indicates a current of y′ when the sink is enabled. Thus, the trigger level of the system may be altered without altering the voltage comparison levels in the remainder of the adaptively clocked circuit.

[0104] As such, the adaptively clocked circuit may be tuned to actuate at various currents, depending on the sink capacity of the programmable current sink 54. In fact, the programmable current sink 54 may be coupled to control circuitry to actuate this programmable or dynamically alterable level.

[0105] FIG. 11 is schematic block diagram indicating how adaptively clocked circuit of the various figures may be used to actuate and dynamically speed up, slow down, or inhibit the clocking to various circuitries. In this exemplary aspect, the digital circuitries 56 and 58 are relayed a clock signal from an adaptively clocked circuit 60. The digital circuitries 62 and 64 are relayed a clock signal derived from another adaptively clocked circuit 62. Thus, during certain power conditions, the digital circuitries may be slowed, stopped, or not affected at all. In one case the digital circuits 62 and 64 may operate at normal speeds while the digital circuits 56 and 58 are inhibited or slowed. Or, the digital circuits 62 and 64 may be slowed while the digital circuits 56 and 58 are inhibited.

[0106] Of course, each adaptively clocked circuit described previously may be used in this system. As such, a controller circuitry may dynamically alter the trigger consumption levels based on states of the other circuitries or other conditions external to the system.

[0107] It should be noted that the preceding diagrams might be joined and used with one another in many different combinations. This specification should be construed as describing the various combinations of power monitors, clock regulators, modal circuitry, and dynamic interaction between a system and the underlying functional units.

[0108] As such, a method and apparatus for an adaptively and dynamically clocking digital circuits and systems is described. In view of the above detailed description of the present invention and associated drawings, other modifications and variations will now become apparent to those skilled in the art. It should also be apparent that such other modifications and variations may be effected without departing from the spirit and scope of the present invention as set forth in the claims which follow.