gem5-stable添加l3 cache

网上找了很多，发现都是改完都有error的。几乎都尝试了，也稍微搞懂了一点点。最后终于成功了。但是对于arm还是有点疑问，大家可以讨论讨论（主要使用的是x86）。

./config/common/Caches.py  这个是新增L3 class定义

复制L2的class，新增L3的class。里面数据根据情况定。

class L3Cache(BaseCache):
    assoc = 64
    hit_latency = 32
    response_latency =32
    mshrs = 32
    tgts_per_mshr = 24
    write_buffers = 16

./config/common/Caches.py 这个是设置连接

修改如下：

        dcache_class, icache_class, l2_cache_class,l3_cache_class = \
            O3_ARM_v7a_DCache, O3_ARM_v7a_ICache, O3_ARM_v7aL2,O3_ARM_v7aL3
    else:
        dcache_class, icache_class, l2_cache_class, l3_cache_class = \
            L1Cache, L1Cache, L2Cache,L3Cache

修改  if options.l2cache:那一个if，在前面增加有l3和l2的情况。L3XBar等会儿定义

if options.l2cache and  options.l3cache:
        system.l2 = l2_cache_class(clk_domain=system.cpu_clk_domain,
                                   size=options.l2_size,
                                   assoc=options.l2_assoc)
	system.l3 = l3_cache_class(clk_domain=system.cpu_clk_domain,
                                   size=options.l3_size,
                                   assoc=options.l3_assoc)

        system.tol2bus = L2XBar(clk_domain = system.cpu_clk_domain)
	system.tol3bus = L3XBar(clk_domain = system.cpu_clk_domain)

        system.l2.cpu_side = system.tol2bus.master
        system.l2.mem_side = system.tol3bus.slave

        system.l3.cpu_side = system.tol3bus.master
        system.l3.mem_side = system.membus.slave
    elif options.l2cache:

./src/mem/XBar.py   定义L3XBar

同样复制L2XBar的class定义，进行修改

class L3XBar(CoherentXBar):
    # 256-bit crossbar by default
    width = 32

    # Assume that most of this is covered by the cache latencies, with
    # no more than a single pipeline stage for any packet.
    frontend_latency = 1
    forward_latency = 0
    response_latency = 1
    snoop_response_latency = 1

./src/cpu/BaseCPU.py 把定义的L3XBar加到cpu里

导入L3XBar，增加函数（也是复制后修改）

from XBar import L3XBar

    def addThreeLevelCacheHierarchy(self, ic, dc, l3c, iwc = None, dwc = None):
        self.addPrivateSplitL1Caches(ic, dc, iwc, dwc)
        self.toL3Bus = L3XBar()
        self.connectCachedPorts(self.toL3Bus)
        self.l3cache = l3c
        self.toL2Bus.master = self.l3cache.cpu_side
        self._cached_ports = ['l3cache.mem_side']

./configs/common/Options.py 最后增加指令--l3cache

   parser.add_option("--l3cache", action="store_true")

重新编译后，就能使用l3cache啦，使用方法同l2。在stats.txt中也会多出关于l3的信息。

希望能和大佬们多多讨论！