Lecture 3 (1/18 Fri.)
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SIMD
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Bit steering
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Instruction sequencing model
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Instruction processing style
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Live in, live out
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Accumulator
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Semantic gap
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ISA translation layer
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Micro-ISA
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Control signals
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Data types in ISA
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RISC versus CISC ISAs
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Open microcode
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Memory organization
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Memory addressability
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Virtual memory
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Big versus little endian
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Programmer visible state
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Load/store vs memory/memory architectures
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Addressing mode
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Orthogonal ISA
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Privilege modes
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Exception and interrupt handling
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Access protection
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并看不懂
- https://www.ece.cmu.edu/~ece447/s15/lib/exe/fetch.php?media=onur-447-spring15-lecture3-isa-tradeoffs-afterlecture.pdf